The present invention relates to power factor correction in voltage applications, and more particularly to control circuits and methods to adapt power factor correction integrated circuits to wide range applications.
Power factor correction ("PFC") pre-regulators are used in various voltage/power applications so that a quasi-sinusoidal current is drawn in-phase with the line voltage, thereby achieving a power factor ("PF") of very close to one. PF is the ratio of the real power transferred to the output and the apparent power (RMS line voltage times RMS line current) drawn from the power main, so that PF of one is desirable. A common technique for achieving power factor correction in low power applications such as lamp ballasts and low-end monitors is the transition mode ("TM") technique, which is used in many different PFC integrated circuit products available from various manufacturers, such as product number L6561 available from SGS Thomson Microelectronics of Carrollton, Tex., and product number MC34262 available from Motorola, Inc., Semiconductor Products Sector of Austin, Tex.
FIG. 1 shows a wide range demonstration board electrical circuit 10. Circuit 10 includes a bridge circuit 20 that delivers a rectified voltage to a boost converter having as its essential elements a boost inductor 48 (in this case, the primary of a transformer), a catch diode 58, an output capacitor 66, and control circuitry that includes a TM PFC integrated circuit ("IC") 9, specifically product number L6561 available from SGS Thomson Microelectronics. The boost converter shown in FIG. 1, which is useful for understanding the operation of the PFC IC 9, uses a switching technique to boost the rectified input voltage from the bridge circuit 20 to a regulated DC output voltage for delivery to a load (not shown) via terminals 68 and 70. The purpose of the PFC IC 9 is to shape its input current in a sinusoidal fashion to be in-phase with the input sinusoidal voltage so as to regulate the DC output voltage.
The circuit 10 operates as follows. An input sinusoidal voltage at terminals 12 and 14 is applied across bridge circuit 20 through fuse 16 and negative temperature coefficient (NTC) device 18. The instantaneous rectified line voltage from the bridge 20 is filtered by input high frequency filter capacitor 22 and applied across a voltage divider 30 having resistor 32, diode 36, resistor 42, capacitor 44, and an auxiliary winding of the boost inductor 48 connected in series. The voltage in the divider 30 between the resistor 32 and diode 36 is applied to V.sub.CC pin 8, and the V.sub.CC input is used internally in the PFC IC 9 to generate an internal reference voltage. Capacitor 34 is connected to V.sub.CC pin 8 for filtering.
In the boost converter, a MOSFET 54 along with a resistor 56 forms a controlled power switch path connected between the boost inductor 48 and ground for energizing and de-energizing the boost induct or 48. The gate of the MOSFET 54 is controlled by the GD output pin 7 of the PFC IC 9 as a function of various voltages applied as inputs to the PFC IC 9. These inputs are ZCD pin 5, COMP pin 2, INV pin 1, and MULT pin 3.
ZCD pin 5 is connected through resistor 46 to the divider 30 at the auxiliary winding of the boost inductor 48 for the purpose of zero current detection and external MOSFET triggering and disabling. Internally, the PFC IC 9 generates a start up signal on output GD pin 7 which turns ON MOSFET 54. Thereafter, the PFC IC 9 internally generates a signal on output GD pin 7 to turn ON the MOSFET 54 as the voltage across the boost inductor 48 reverses. This feature allows transition mode operation.
COMP pin 2 and INV pin 1 are connected to a point between resistors 62 and 64, which form a voltage divider 60 across the output of the circuit 10. The PFC IC 9 compares a portion of the boosted output DC voltage at the terminals 68 and 70 with its internal reference voltage to maintain the pre-regulator output DC voltage constant. A feedback capacitor 50 is connected between pins 1 and 2 for frequency compensation. The PFC IC 9 uses a two-level overvoltage protection scheme, initially decreasing the gate voltage of MOSFET 54 at GD pin 7 to provide a "soft braking" action when a rising output voltage is detected, and then turning OFF the MOSFET 54 to provide a "heavy braking" action if a continuing rise in the output voltage is detected. The voltage across the resistor 56 is applied to the CS input pin 4 of the PFC IC 9 to determine the exact time when the MOSFET 54 is to be turned OFF.
MULT pin 3 is connected to a point between resistors 26 and 28 in a voltage divider 24 to receive a portion of the instantaneous rectified line voltage. The PFC IC 9 uses the MULT input to set the peak current of the MOSFET 54 cycle by cycle. Typically, the MULT input signal is shaped like a rectified sinusoid. Capacitor 40 is connected to MULT pin 3 for filtering.
The various circuits and operation of the integrated circuit 9 are further described by Claudio Adragna in Application Note AN966: L6561 Enhanced Transition Mode Power Factor Corrector, SGS-Thompson Microelectronics, March 1998.
Transition mode PFC ICs from various manufacturers are attractive to product designers since they are placed in relatively simple circuits that require relatively few external components and a relatively low value of boost inductance. Applications that use PFC ICs in an upconverter design generally use a sense resistor divider off the rectified line, such as for example, circuit 10 of FIG. 1, which uses the divider 24 to provide the MULT input voltage at pin 3. Although this signal is a rectified sine wave, distortion occurs at the zero crossing of the input line current. This zero crossing distortion is negligible for low power, small input voltage range applications, but becomes quite large if the load power range is large and/or the input voltage range is large. Such wide range applications can cause input line current total harmonic distortion in excess of 10%, which is generally undesirable.